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1. general description the pca9547 is an octal bidirectional translating multiplexer controlled by the i 2 c-bus. the scl/sda upstream pair fans out to eight downstream pairs, or channels. only one scx/sdx channel can be selected at a time, determined by the contents of the programmable control register. the device powers up with channel 0 connected, allowing immediate communication between the master and downstream devices on that channel. an active low reset input allows the pca9547 to recover from a situation where one of the downstream i 2 c-buses is stuck in a low state. pulling the reset pin low resets the i 2 c-bus state machine causing all the channels to be deselected, except channel 0 so that the master can regain control of the bus. the pass gates of the multiplexers are constructed such that the v dd pin can be used to limit the maximum high voltage which will be passed by the pca9547. this allows the use of different bus voltages on each pair, so that 1.8 v, 2.5 v, or 3.3 v parts can communicate with 5 v parts without any additional protection. external pull-up resistors pull the bus up to the desired voltage level for each channel. all i/o pins are 5 v tolerant. 2. features n 1-of-8 bidirectional translating multiplexer n i 2 c-bus interface logic; compatible with smbus standards n active low reset input n 3 address pins allowing up to 8 devices on the i 2 c-bus n channel selection via i 2 c-bus, one channel at a time n power-up with all channels deselected except channel 0 which is connected n low r on multiplexers n allows voltage level translation between 1.8 v, 2.5 v, 3.3 v and 5 v buses n no glitch on power-up n supports hot insertion n low standby current n operating power supply voltage range of 2.3 v to 5.5 v n 5 v tolerant inputs n 0 hz to 400 khz clock frequency n esd protection exceeds 2000 v hbm per jesd22-a114, 200 v mm per jesd22-a115, and 1000 v cdm per jesd22-c101 n latch-up testing is done to jedec standard jesd78 which exceeds 100 ma n packages offered: so24, tssop24, hvqfn24 pca9547 8-channel i 2 c-bus multiplexer with reset rev. 03 10 july 2009 product data sheet
pca9547_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 10 july 2009 2 of 26 nxp semiconductors pca9547 8-channel i 2 c-bus multiplexer with reset 3. ordering information 3.1 ordering options table 1. ordering information type number package name description version pca9547d so24 plastic small outline package; 24 leads; body width 7.5 mm sot137-1 PCA9547PW tssop24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm sot355-1 pca9547bs hvqfn24 plastic thermal enhanced very thin quad ?at package; no leads; 24 terminals; body 4 4 0.85 mm sot616-1 table 2. ordering options type number topside mark temperature range pca9547d pca9547d t amb = - 40 c to +85 c PCA9547PW pca9547 t amb = - 40 c to +85 c pca9547bs 9547 t amb = - 40 c to +85 c
pca9547_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 10 july 2009 3 of 26 nxp semiconductors pca9547 8-channel i 2 c-bus multiplexer with reset 4. block diagram fig 1. block diagram of pca9547 switch control logic pca9547 reset circuit 002aaa961 sc0 sc1 sc2 sc3 sc4 sc5 sc6 sc7 sd0 sd1 sd2 sd3 sd4 sd5 sd6 sd7 v ss v dd reset i 2 c-bus control input filter scl sda a0 a1 a2
pca9547_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 10 july 2009 4 of 26 nxp semiconductors pca9547 8-channel i 2 c-bus multiplexer with reset 5. pinning information 5.1 pinning fig 2. pin con?guration for so24 fig 3. pin con?guration for tssop24 fig 4. pin con?guration for hvqfn24 (transparent top view) pca9547d a0 v dd a1 sda reset scl sd0 a2 sc0 sc7 sd1 sd7 sc1 sc6 sd2 sd6 sc2 sc5 sd3 sd5 sc3 sc4 v ss sd4 002aaa958 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 18 17 20 19 22 21 24 23 PCA9547PW a0 v dd a1 sda reset scl sd0 a2 sc0 sc7 sd1 sd7 sc1 sc6 sd2 sd6 sc2 sc5 sd3 sd5 sc3 sc4 v ss sd4 002aaa959 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 18 17 20 19 22 21 24 23 002aaa960 pca9547bs transparent top view sc5 sd2 sc2 sd6 sc1 sc6 sd1 sd7 sc0 sc7 sd0 a2 sd3 sc3 v ss sd4 sc4 sd5 reset a1 a0 v dd sda scl terminal 1 index area 6 13 5 14 4 15 3 16 2 17 1 18 7 8 9 10 11 12 24 23 22 21 20 19
pca9547_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 10 july 2009 5 of 26 nxp semiconductors pca9547 8-channel i 2 c-bus multiplexer with reset 5.2 pin description [1] hvqfn24 package die supply ground is connected to both the v ss pin and the exposed center pad. the v ss pin must be connected to supply ground for proper device operation. for enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the pcb in the thermal pad region. table 3. pin description symbol pin description so24, tssop24 hvqfn24 a0 1 22 address input 0 a1 2 23 address input 1 reset 3 24 active low reset input sd0 4 1 serial data output 0 sc0 5 2 serial clock output 0 sd1 6 3 serial data output 1 sc1 7 4 serial clock output 1 sd2 8 5 serial data output 2 sc2 9 6 serial clock output 2 sd3 10 7 serial data output 3 sc3 11 8 serial clock output 3 v ss 12 9 [1] supply ground sd4 13 10 serial data output 4 sc4 14 11 serial clock output 4 sd5 15 12 serial data output 5 sc5 16 13 serial clock output 5 sd6 17 14 serial data output 6 sc6 18 15 serial clock output 6 sd7 19 16 serial data output 7 sc7 20 17 serial clock output 7 a2 21 18 address input 2 scl 22 19 serial clock line sda 23 20 serial data line v dd 24 21 supply voltage
pca9547_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 10 july 2009 6 of 26 nxp semiconductors pca9547 8-channel i 2 c-bus multiplexer with reset 6. functional description 6.1 device addressing following a start condition, the bus master must output the address of the slave it is accessing. the address of the pca9547 is shown in figure 5 . to conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled high or low. the last bit of the slave address de?nes the operation to be performed. when set to logic 1 a read is selected, while a logic 0 selects a write operation. 6.2 control register following the successful acknowledgement of the slave address, the bus master will send a byte to the pca9547, which will be stored in the control register. if multiple bytes are received by the pca9547, it will save the last byte received. this register can be written and read via the i 2 c-bus. 6.2.1 control register de?nition a scx/sdx downstream pair, or channel, is selected by the contents of the control register. this register is written after the pca9547 has been addressed. the 4 lsbs of the control byte are used to determine which channel is to be selected. when a channel is selected, the channel will become active after a stop condition has been placed on the i 2 c-bus. this ensures that all scx/sdx lines will be in a high state when the channel is made active, so that no false conditions are generated at the time of connection. fig 5. slave address 002aaa962 1 1 1 0 a2 a1 a0 r/w fixed hardware selectable fig 6. control register 002aaa963 x x x x b3 b2 b1 b0 channel selection bits (read/write) 76543210 enable bit
pca9547_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 10 july 2009 7 of 26 nxp semiconductors pca9547 8-channel i 2 c-bus multiplexer with reset 6.3 reset input the reset input is an active low signal which may be used to recover from a bus fault condition. by asserting this signal low for a minimum of t w(rst)l , the pca9547 will reset its register and i 2 c-bus state machine and will deselect all channels except channel 0. the reset input must be connected to v dd through a pull-up resistor. 6.4 power-on reset when power is applied to v dd , an internal power-on reset (por) holds the pca9547 in a reset condition until v dd has reached v por . at this point, the reset condition is released and the pca9547 register and i 2 c-bus state machine are initialized to their default states, causing all the channels to be deselected except channel 0. thereafter, v dd must be lowered below 0.2 v to reset the device. table 4. control register write = channel selection; read = channel status d7 d6 d5 d4 b3 b2 b1 b0 command x x x x 0 x x x no channel selected x x x x 1 0 0 0 channel 0 enabled x x x x 1 0 0 1 channel 1 enabled x x x x 1 0 1 0 channel 2 enabled x x x x 1 0 1 1 channel 3 enabled x x x x 1 1 0 0 channel 4 enabled x x x x 1 1 0 1 channel 5 enabled x x x x 1 1 1 0 channel 6 enabled x x x x 1 1 1 1 channel 7 enabled 00001000 channel 0 enabled; power-up/reset default state
pca9547_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 10 july 2009 8 of 26 nxp semiconductors pca9547 8-channel i 2 c-bus multiplexer with reset 6.5 voltage translation the pass gate transistors of the pca9547 are constructed such that the v dd voltage can be used to limit the maximum voltage that will be passed from one i 2 c-bus to another. figure 7 shows the voltage characteristics of the pass gate transistors (note that the pca9547 is only tested at the points speci?ed in section 10 static char acter istics of this data sheet). in order for the pca9547 to act as a voltage translator, the v o(mux) voltage should be equal to, or lower than the lowest bus voltage. for example, if the main bus was running at 5 v, and the downstream buses were 3.3 v and 2.7 v, then v o(mux) should be equal to or below 2.7 v to effectively clamp the downstream bus voltages. looking at figure 7 , we see that v o(mux)(max) will be at 2.7 v when the pca9547 supply voltage is 3.5 v or lower so the pca9547 supply voltage could be set to 3.3 v. pull-up resistors can then be used to bring the bus voltages to their appropriate levels (see figure 14 ). more information can be found in application note an262, pca954x family of i 2 c/smbus multiplexers and switches . (1) maximum (2) typical (3) minimum fig 7. pass gate voltage as a function of supply voltage v dd (v) 2.0 5.5 4.5 3.0 4.0 002aab802 3.0 2.0 4.0 5.0 v o(mux) (v) 1.0 3.5 5.0 2.5 (1) (2) (3)
pca9547_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 10 july 2009 9 of 26 nxp semiconductors pca9547 8-channel i 2 c-bus multiplexer with reset 7. characteristics of the i 2 c-bus the i 2 c-bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 7.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see figure 8 ). 7.1.1 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line while the clock is high is de?ned as the start condition (s). a low-to-high transition of the data line while the clock is high is de?ned as the stop condition (p) (see figure 9 .) fig 8. bit transfer mba607 data line stable; data valid change of data allowed sda scl fig 9. de?nition of start and stop conditions mba608 sda scl p stop condition s start condition
pca9547_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 10 july 2009 10 of 26 nxp semiconductors pca9547 8-channel i 2 c-bus multiplexer with reset 7.2 system con?guration a device generating a message is a transmitter; a device receiving is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves (see figure 10 ). 7.3 acknowledge the number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. each byte of eight bits is followed by one acknowledge bit. the acknowledge bit is a high level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse; set-up and hold times must be taken into account. a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. fig 10. system con?guration 002aaa966 master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver sda scl i 2 c-bus multiplexer slave fig 11. acknowledgement on the i 2 c-bus 002aaa987 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
pca9547_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 10 july 2009 11 of 26 nxp semiconductors pca9547 8-channel i 2 c-bus multiplexer with reset 7.4 bus transactions data is transmitted to the pca9547 control register using the write mode as shown in figure 12 . data is read from pca9547 using the read mode as shown in figure 13 . fig 12. write control register fig 13. read control register 002aaa988 xxxxb3b2b1b0 1 1 0 a2 a1 a0 0 a s 1 a p slave address start condition r/w acknowledge from slave acknowledge from slave control register sda stop condition 002aaa989 xxxxb3b2b1b0 1 1 0 a2 a1 a0 1 a s 1 na p slave address start condition r/w acknowledge from slave no acknowledge from master control register sda stop condition last byte
pca9547_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 10 july 2009 12 of 26 nxp semiconductors pca9547 8-channel i 2 c-bus multiplexer with reset 8. application design-in information fig 14. typical application pca9547 sd0 sc0 sd1 sc1 a1 a0 v ss sda scl reset v dd = 3.3 v v dd = 2.7 v to 5.5 v i 2 c-bus/smbus master 002aaa965 sda scl channel 0 channel 1 sd2 sc2 channel 2 sd3 sc3 channel 3 a2 sd4 sc4 v = 2.7 v to 5.5 v sd5 sc5 channel 4 channel 5 sd6 sc6 channel 6 v = 2.7 v to 5.5 v sd7 sc7 channel 7 v = 2.7 v to 5.5 v v = 2.7 v to 5.5 v v = 2.7 v to 5.5 v v = 2.7 v to 5.5 v v = 2.7 v to 5.5 v v = 2.7 v to 5.5 v
pca9547_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 10 july 2009 13 of 26 nxp semiconductors pca9547 8-channel i 2 c-bus multiplexer with reset 9. limiting values [1] the performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. the maximum junction temperature of this integrated circuit should not exceed 125 c. table 5. limiting values in accordance with the absolute maximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd supply voltage - 0.5 +7.0 v v i input voltage - 0.5 +7.0 v i i input current - 20 +20 ma i o output current - 25 +25 ma i dd supply current - 100 +100 ma i ss ground supply current - 100 +100 ma p tot total power dissipation - 400 mw t stg storage temperature - 60 +150 c t amb ambient temperature - 40 +85 c
pca9547_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 10 july 2009 14 of 26 nxp semiconductors pca9547 8-channel i 2 c-bus multiplexer with reset 10. static characteristics [1] for operation between published voltage ranges, refer to the worst-case parameter in both ranges. [2] v dd must be lowered to 0.2 v in order to reset part. table 6. static characteristics at v dd = 2.3 v to 3.6 v v ss = 0 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. see t ab le 7 on page 15 for v dd = 4.5 v to 5.5 v. [1] symbol parameter conditions min typ max unit supply v dd supply voltage 2.3 - 3.6 v i dd supply current operating mode; v dd = 3.6 v; no load; v i =v dd or v ss ; f scl = 100 khz -2050 m a i stb standby current standby mode; v dd = 3.6 v; no load; v i =v dd or v ss - 0.1 2 m a v por power-on reset voltage no load; v i =v dd or v ss [2] - 1.6 2.1 v input scl; input/output sda v il low-level input voltage - 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -6 v i ol low-level output current v ol = 0.4 v 3 - - ma v ol = 0.6 v 6 - - ma i l leakage current v i =v dd or v ss - 1-+1 m a c i input capacitance v i =v ss -1419pf select inputs a0, a1, a2, reset v il low-level input voltage - 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -v dd + 0.5 v i li input leakage current pin at v dd or v ss - 1-+1 m a c i input capacitance v i =v ss -25 pf pass gate r on on-state resistance multiplexer; v dd = 3.6 v; v o = 0.4 v; i o =15ma 51130 w multiplexer; v dd = 2.3 v to 2.7 v; v o = 0.4 v; i o =10ma 71655 w v o(mux) multiplexer output voltage v i(mux) =v dd = 3.3 v; i o(mux) = - 100 m a - 1.9 - v v i(mux) =v dd = 3.0 v to 3.6 v; i o(mux) = - 100 m a 1.6 - 2.8 v v o(mux) =v dd = 2.5 v; i o(mux) = - 100 m a - 1.5 - v v o(mux) =v dd = 2.3 v to 2.7 v; i o(mux) = - 100 m a 0.9 - 2.0 v i l leakage current v i =v dd or v ss - 1-+1 m a c io input/output capacitance v i =v ss -35 pf
pca9547_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 10 july 2009 15 of 26 nxp semiconductors pca9547 8-channel i 2 c-bus multiplexer with reset [1] for operation between published voltage ranges, refer to the worst-case parameter in both ranges. [2] v dd must be lowered to 0.2 v in order to reset part. table 7. static characteristics at v dd = 4.5 v to 5.5 v v ss = 0 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. see t ab le 6 on page 14 for v dd = 2.3 v to 3.6 v. [1] symbol parameter conditions min typ max unit supply v dd supply voltage 4.5 - 5.5 v i dd supply current operating mode; v dd = 5.5 v; no load; v i =v dd or v ss ; f scl = 100 khz - 65 100 m a i stb standby current standby mode; v dd = 5.5 v; no load; v i =v dd or v ss - 0.6 2 m a v por power-on reset voltage no load; v i =v dd or v ss [2] - 1.7 2.1 v input scl; input/output sda v il low-level input voltage - 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -6 v i ol low-level output current v ol = 0.4 v 3 - - ma v ol = 0.6 v 6 - - ma i il low-level input current v i =v ss - 1- +1 m a i ih high-level input current v i =v ss - 1- +1 m a c i input capacitance v i =v ss -1419pf select inputs a0, a1, a2, reset v il low-level input voltage - 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -v dd + 0.5 v i li input leakage current pin at v dd or v ss - 1- +1 m a c i input capacitance v i =v ss -25 pf pass gate r on on-state resistance multiplexer; v dd = 4.5 v to 5.5 v; v o = 0.4 v; i o =15ma 4924 w v o(mux) multiplexer output voltage v i(mux) =v dd = 5.0 v; i o(mux) = - 100 m a - 3.6 - v v i(mux) =v dd = 4.5 v to 5.5 v; i o(mux) = - 100 m a 2.6 - 4.5 v i l leakage current v i =v dd or v ss - 1- +1 m a c io input/output capacitance v i =v ss -35 pf
pca9547_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 10 july 2009 16 of 26 nxp semiconductors pca9547 8-channel i 2 c-bus multiplexer with reset 11. dynamic characteristics [1] pass gate propagation delay is calculated from the 20 w typical r on and the 15 pf load capacitance. [2] after this period, the ?rst clock pulse is generated. [3] a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ih(min) of the scl signal) in order to bridge the unde?ned region of the falling edge of scl. [4] c b = total capacitance of one bus line in pf. [5] measurements taken with 1 k w pull-up resistor and 50 pf load. table 8. dynamic characteristics symbol parameter conditions standard-mode i 2 c-bus fast-mode i 2 c-bus unit min max min max t pd propagation delay from sda to sdx, or scl to scx - 0.3 [1] - 0.3 [1] ns f scl scl clock frequency 0 100 0 400 khz t buf bus free time between a stop and start condition 4.7 - 1.3 - m s t hd;sta hold time (repeated) start condition [2] 4.0 - 0.6 - m s t low low period of the scl clock 4.7 - 1.3 - m s t high high period of the scl clock 4.0 - 0.6 - m s t su;sta set-up time for a repeated start condition 4.7 - 0.6 - m s t su;sto set-up time for stop condition 4.0 - 0.6 - m s t hd;dat data hold time 0 [3] 3.45 0 [3] 0.9 m s t su;dat data set-up time 250 - 100 - ns t r rise time of both sda and scl signals - 1000 20 + 0.1c b [4] 300 ns t f fall time of both sda and scl signals - 300 20 + 0.1c b [4] 300 ns c b capacitive load for each bus line - 400 - 400 pf t sp pulse width of spikes that must be suppressed by the input ?lter - 50 - 50 ns t vd;dat data valid time high-to-low [5] -1 - 1 m s low-to-high [5] - 0.6 - 0.6 m s t vd;ack data valid acknowledge time - 1 - 1 m s reset t w(rst)l low-level reset time 4 - 4 - ns t rst reset time sda clear 500 - 500 - ns t rec(rst) reset recovery time 0 - 0 - ns
pca9547_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 10 july 2009 17 of 26 nxp semiconductors pca9547 8-channel i 2 c-bus multiplexer with reset fig 15. de?nition of timing on the i 2 c-bus t sp t buf t hd;sta p p s t low t r t hd;dat t f t high t su;dat t su;sta sr t hd;sta t su;sto sda scl 002aaa986 fig 16. de?nition of reset timing sda scl 002aac314 50 % 70 % 50 % 50 % t rec(rst) t w(rst)l reset start t rst ack or read cycle
pca9547_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 10 july 2009 18 of 26 nxp semiconductors pca9547 8-channel i 2 c-bus multiplexer with reset 12. package outline fig 17. so24 package outline (sot137-1) unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v q references outline version european projection issue date iec jedec jeita mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 sot137-1 x 12 24 w m q a a 1 a 2 b p d h e l p q detail x e z c l v m a 13 (a ) 3 a y 0.25 075e05 ms-013 pin 1 index 0.1 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.61 0.60 0.30 0.29 0.05 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 e 1 0 5 10 mm scale so24: plastic small outline package; 24 leads; body width 7.5 mm sot137-1 99-12-27 03-02-19
pca9547_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 10 july 2009 19 of 26 nxp semiconductors pca9547 8-channel i 2 c-bus multiplexer with reset fig 18. tssop24 package outline (sot355-1) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 7.9 7.7 4.5 4.3 0.65 6.6 6.2 0.4 0.3 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot355-1 mo-153 99-12-27 03-02-19 0.25 0.5 0.2 w m b p z e 112 24 13 pin 1 index q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a d y 0 2.5 5 mm scale tssop24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm sot355-1 a max. 1.1
pca9547_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 10 july 2009 20 of 26 nxp semiconductors pca9547 8-channel i 2 c-bus multiplexer with reset fig 19. hvqfn24 package outline (sot616-1) 0.5 1 0.2 a 1 e h b unit y e references outline version european projection issue date iec jedec jeita mm 4.1 3.9 d h 2.25 1.95 y 1 4.1 3.9 2.25 1.95 e 1 2.5 e 2 2.5 0.30 0.18 c 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot616-1 mo-220 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot616-1 hvqfn24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 712 24 19 18 13 6 1 x d e c b a e 2 01-08-08 02-10-22 terminal 1 index area terminal 1 index area a c c b v m w m 1/2 e 1/2 e e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1)
pca9547_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 10 july 2009 21 of 26 nxp semiconductors pca9547 8-channel i 2 c-bus multiplexer with reset 13. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 13.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 13.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities
pca9547_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 10 july 2009 22 of 26 nxp semiconductors pca9547 8-channel i 2 c-bus multiplexer with reset 13.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 20 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 9 and 10 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 20 . table 9. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 10. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pca9547_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 10 july 2009 23 of 26 nxp semiconductors pca9547 8-channel i 2 c-bus multiplexer with reset for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 14. abbreviations msl: moisture sensitivity level fig 20. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 11. abbreviations acronym description cdm charged device model esd electrostatic discharge hbm human body model i 2 c-bus inter-integrated circuit bus lsb least signi?cant bit mm machine model pcb printed-circuit board smbus system management bus
pca9547_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 10 july 2009 24 of 26 nxp semiconductors pca9547 8-channel i 2 c-bus multiplexer with reset 15. revision history table 12. revision history document id release date data sheet status change notice supersedes pca9547_3 20090710 product data sheet - pca9547_2 modi?cations: ? the format of this data sheet has been redesigned to comply with the new identity guidelines of nxp semiconductors. ? legal texts have been adapted to the new company name where appropriate. ? t ab le 5 limiting v alues , t ab le note [1] : changed from ... should not exceed 150 c. to ... should not exceed 125 c. ? t ab le 7 static char acter istics at v dd = 4.5 v to 5.5 v , sub-section input scl; input/output sda: C changed i il min value from 1 m a to - 1 m a C changed i il max value from 1 m a to +1 m a C changed i ih min value from 1 m a to - 1 m a C changed i ih max value from 1 m a to +1 m a ? t ab le 8 dynamic char acter istics : C symbol t f : changed unit from m s to ns C symbol c b : changed unit from m s to pf ? updated soldering information. pca9547_2 20060912 product data sheet - pca9547_1 pca9547_1 (9397 750 13369) 20051005 product data sheet - -
pca9547_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 10 july 2009 25 of 26 nxp semiconductors pca9547 8-channel i 2 c-bus multiplexer with reset 16. legal information 16.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 16.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 16.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. export control this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 16.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. 17. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors pca9547 8-channel i 2 c-bus multiplexer with reset ? nxp b.v. 2009. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 10 july 2009 document identifier: pca9547_3 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 functional description . . . . . . . . . . . . . . . . . . . 6 6.1 device addressing . . . . . . . . . . . . . . . . . . . . . . 6 6.2 control register . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2.1 control register de?nition . . . . . . . . . . . . . . . . . 6 6.3 reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.4 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.5 voltage translation . . . . . . . . . . . . . . . . . . . . . . 8 7 characteristics of the i 2 c-bus. . . . . . . . . . . . . . 9 7.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.1.1 start and stop conditions . . . . . . . . . . . . . . 9 7.2 system con?guration . . . . . . . . . . . . . . . . . . . 10 7.3 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.4 bus transactions . . . . . . . . . . . . . . . . . . . . . . . 11 8 application design-in information . . . . . . . . . 12 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13 10 static characteristics. . . . . . . . . . . . . . . . . . . . 14 11 dynamic characteristics . . . . . . . . . . . . . . . . . 16 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 18 13 soldering of smd packages . . . . . . . . . . . . . . 21 13.1 introduction to soldering . . . . . . . . . . . . . . . . . 21 13.2 wave and re?ow soldering . . . . . . . . . . . . . . . 21 13.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 21 13.4 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 22 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 23 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . 24 16 legal information. . . . . . . . . . . . . . . . . . . . . . . 25 16.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 25 16.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 16.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 16.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 17 contact information. . . . . . . . . . . . . . . . . . . . . 25 18 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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